The present invention relates generally to non-volatile memories and in particular the present invention relates to erase operations in a flash memory device.
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM). RAM has traditionally been used as main memory in a computer environment. Most RAM is volatile, which means that it requires periodic refresh of electricity to maintain its contents. Yet another type memory is a flash memory. A flash memory is a type of memory that is non-volatile. That is, flash memory is a type of memory that retains data even without a periodic refresh of electricity. Flash memory has many applications. For example, many modern computers have their basic I/O system bios stored on a flash memory chip, so that it can be easily updated if necessary. Moreover, some digital systems have replaced conventional mass storage devices with flash memory devices. Specifically, some conventional hard drives in personal computers have been replaced with flash memory.
A typical flash memory comprises a memory array that is separated into blocks of memory cells (cells). Each block of cells is arranged in a row and column fashion Each cell includes a floating gate field-effect transistor capable of holding a charge. Each cell can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by an erase operation. Thus, the data in a cell is determined by the presence or absence of the charge in the floating gate.
The state of a Flash memory cell is read or verified using a reference cell current. That is, a reference non-volatile memory cell is coupled to a sense amplifier circuit via a reference bit line. The cell to be verified is also coupled to the sense amplifier circuit via a second bit line. A differential current between the bit lines is detected, and the programmed state of the cell is determined. For example, the reference cell may be programmed to an intermediate state such that it conducts about half the current conducted by a fully programmed memory cell, such that if the cell to be read is programmed, it conducts more current than the reference memory cell, and if the cell to be read is erased, it conducts less current than the reference cell.
To program a memory cell, a high positive voltage such as 12 volts is applied to the control gate of the cell. In addition, a moderate positive voltage such as 6 to 9 volts is applied to the drain while a source voltage and a substrate voltage are at ground level. These conditions result in the inducement of hot electron injection in the channel region near the drain region of the memory cell. These high-energy electrons travel through the thin gate oxide towards the positive voltage present on the control gate and collect on the floating gate. The electrons remain on the floating gate and function to increase the effective threshold voltage of the cell as compared to a cell that has not been programmed.
In flash memories, cells are erased in blocks. This is achieved by putting a negative voltage such as xe2x88x9210 to xe2x88x9217 volts on word lines coupled to the control gates of all the cells in a block of cells and coupling the source connection of the block to a Vcc (power supply) such as 5 volts, or higher for a period of time. This is usually done as a pulse or a series of pulses. Each pulse creates a field that removes electrons from the floating gates of the memory elements. The speed in which a cell is erased, i.e. the number of pulses needed to erase the cell, is dependant on many varying conditions including voltage level of pulses, length of pulses and temperature. It is common to have a flash memory block in which individual memory cells erase at different rates. In this situation, typically the slowest bit in the block dictates the level of erasure of all the cells in the block. This can cause the other cells in the block to become over-erased. If, for example, a typical memory cells require 10 pulses to erase and the slowest memory cell in an erasable block requires 30 pulses to erase, in erasing the slowest cells, the typical cells are subject to an extra 20 erase pulses that could potentially cause them to become over-erased.
An over-erased cell is a cell that has been erased past a certain point. An over-erased cell becomes depleted. That is, too many electrons are removed from the floating gate, causing a floating gate voltage to become more positive than the threshold of the cell. The cell, therefore, cannot be turned off, even if the control gate is at a ground potential. Moreover, an over-erased cell can cause all memory cells coupled to the same column to be read as erased cells, even though they may be programmed.
To limit the amount of over-erased cells in a block of flash memory, an erase operation comprising a pre-program cycle, an erase cycle, and a soft program cycle, is generally performed. During a pre-program cycle, all the cells in a block are first programmed above a predetermined level. This is done so that the floating gates of all the cells in the block start out with approximately the same amount of charge. The erase cycle then applies an erase pulse to the block and verifies each cell row by row to determine if all the cells are in an erased state. The erase cycle is repeated until all the cells have been verified as being erased. The soft programming cycle, or, as it is sometimes referred to, the voltage (Vt) distribution cycle, then checks each column (bit line) in the block for current levels that would indicate if an over-erased cell is coupled to the bit line. If an over-erased cell is detected in a bit line, a soft program (soft programming pulse) is systematically applied to the control gates of the cells coupled to the bit line until the current can no longer be detected.
Although a soft program cycle can be used to recover over-erased cells, it is however, desired to reduce the number of over-erased cells before a soft program cycle is applied, because some cells that are over-erased cannot be recovered. Moreover, the integrity of cells that are over-erased and recovered can be diminished with each over-erasure.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flash memory with an improved process for erasing a block of flash memory having a small number of cells that are slow to erase as compared to other cells in the block.
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention, and will be understood by reading and studying the following specification.
In one embodiment, a method of operating a flash memory is disclosed. The method comprising, erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculating an acceptable number of additional erase pulses which could be applied to the memory block.
In another embodiment, a method of operating a flash memory is disclosed. The method comprising, applying at least one erase pulse to the block, wherein the block has a plurality of memory cells arranged in rows, verifying each row to determine if the memory cells associated with each row are erased after each erase pulse and completing erase of the block when a predetermined number of rows in the block have been verified as being erased, wherein the predetermined number of rows is less than the total number of rows in the block.
In another embodiment, a method of operating a non-volatile memory is disclosed. The method comprising, applying at least one erase pulse to a block of flash memory cells, wherein the block of memory cells is arranged in rows, verifying if each row is erased in the block after each erase pulse is applied, counting the number of erase pulses used to verify a predetermined number of rows have been erased in the block and applying a predetermined number of erase pulses to the block to try to erase the rows that have not been verified as being erased, wherein the predetermined number of erase pulses is a fraction of the number of erase pulses used to verify the predetermined number of rows.
In another embodiment, a method of performing an erase operation on a flash memory block is disclosed. The method comprising, pre-charging flash memory cells arranged in rows in the block to a predetermined level, applying at least one first stage erase pulse to the block, verifying if each memory cell is erased by row after each first stage erase pulse is applied to the block, counting a first number of pulses applied to the block, wherein the first number of pulses applied to the block is the number of pulses used to verify a majority of rows in the block have been erased, calculating a second number based on a fraction of the first number, wherein the second number is a maximum number of additional second stage erase pulses that may be applied to the block to try and erase the memory cells in the rows not yet verified as being erased, applying at least one second stage erase pulse to the block, verifying if each memory cell is erased by row after each second stage erase pulse is applied to the block and completing erase of the block when either the second number of second stage erase pulses have been applied to the block or all the rows have been verified as being erased.
In another embodiment, a flash memory device comprises a memory array, a controller and a register. The memory array has a plurality of blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory array and the register is coupled to the controller to track the erase status of each row of memory cells.
In another embodiment, a non-volatile memory device comprises a plurality of memory arrays, a controller and a register array. Each memory array has a plurality of blocks of flash memory cells. Moreover, the flash memory cells in each block are arranged in rows. The controller is used to control memory operations to the memory arrays. The controller stores data in the register array to track rows of memory cells in blocks verified as being erased.
In another embodiment, a flash memory device comprises, a memory array and a control circuit. The memory array has a plurality of erasable blocks of memory cells. The memory cells in each block are arranged in rows. The control circuit is used to control memory operations to the memory array. Specifically, the control circuit applies a first number of erase pulses to a block being erased in a first stage and a second number of erase pulses to the block in a second stage. The number of erase pulses applied in the second stage is based on the number of erase pulses needed in the first stage to verify a predetermined number of rows in the block have been erased.
In yet another embodiment, a flash memory system comprises, a processor, a plurality of memory arrays, a controller and a plurality of registers. The processor is used to provide external erase commands. Each memory array has a plurality of erasable blocks of flash memory cells. The memory cells in each block are arranged in rows. The controller is used to receive the external erase commands from the processor. Moreover, the controller performs erase operations on the blocks of memory cells in the plurality of memory arrays. The plurality of registers are coupled to the controller to track rows of memory cells verified as being erased. Each register is associated with one of the memory arrays. In addition, each register has a plurality of register sub-blocks. Each register sub-block is associated with a block of memory cells. Moreover, each sub-block has a register memory cell for each row in its associated block of memory cells.